I am NOT SWISS and I DON'T SOUND SWISS either!

i'm a crazy welsh person (who grew up and lives in switzerland)





Wednesday, May 30, 2007

confused

it's been a year and a half since i last used VHDL, i'm used to verilog now. so, looking at a piece of VHDL i get confused: why are there blocking assignments in a block that's clearly not meant to be sequential?! the process is called 'memless'... took me a while to realise that there's no such thing in VHDL, all assignments use the '<=' operator...

:-S

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posted by Vickster at 14:48.

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